Analog Design Engineer Phase Lock Loop

Company: Advanced Micro Devices
Location: Santa Clara
Posted on: February 2, 2025

Job Description:

WHAT YOU DO AT AMD CHANGES EVERYTHINGWe care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.AMD together we advance.THE ROLE:AMD is searching for an experienced Circuit Design Engineer to join the fast-growing PLL design team, responsible for defining, specifying, and implementing current and future advanced PLL IPs powering AMD products.Join a dynamic team and give a boost to your personal career in a challenging and fascinating area! Looking forward to welcoming you to the team!THE PERSON:

• Solid knowledge of Mixed Signal Circuit Design in FinFET technology specifically in PLLs and associated subblocks including VCO, charge-pump, dividers, state machines, LDO, feedback and compensation techniques, bandgap, TDC, interpolator circuits, high speed buffers, etc.
• Solid knowledge of industry standard tools and practices for analog circuit design.
• Good knowledge in Physical design, STA, methodology scripts (Tcl), knowledge on Perl, Python.
• Quality-oriented mindset.
• Strong and effective communication skills and team spirit.KEY RESPONSIBILITIES:
  • Design of complex building blocks of a PLL including architecture development and transistor level circuit design.
  • Run pre-tapeout verification flows to confirm design meets performance, power, reliability and timing requirements.
  • Work closely with mask design engineers to deliver the physical design as well as define production/bench-level test plans with post-silicon characterization groups for silicon evaluation to ensure interlocked and high-quality execution.
  • Lead/mentor junior engineers.PREFERRED EXPERIENCE:
    • Strong experience in the semiconductor industry.
    • Experience in FinFET & Dual Patterning nodes such as 16/14/10/7nm.
    • Hands-on design experience in performance analog and hybrid Phase Locked Loops, analog-to-digital (ADC), digital-to-analog (DAC) data converter, VCO, LDO, bandgap, charge pump, op-amps, interpolator circuits.
    • Experience with Digital PLL techniques, TDC or DSP and control theory experience related to digital PLLs, Dual charge-pump PLL designs, Fractional-N PLLs, spread-spectrum PLLs is a plus.
    • Proficient with Cadence custom circuit design tools like ADE-L and ADE-XL and running Monte-Carlo, noise, aging, EM and IR drop simulations and stability analysis. Helic/EMX is a plus.
    • Good experience with simulation tools such as Spectre, Hspice, AFS, and MATLAB, System Verilog, Python.
    • Capable of understanding DRC and LVS results with verification tools (Calibre, ICV, or like).
    • Proficiency in scripting languages like Perl, Python, MATLAB, etc. is a plus.
    • Able to work effectively in a team, with good interpersonal skills, enthusiasm and positive energy.
    • Possess strong analytical/problem-solving skills and pronounced attention to details.
    • Must be a self-starter, and able to independently drive tasks to completion.ACADEMIC CREDENTIALS:
      • Master's in electrical engineering or equivalent preferred.LOCATION: Santa Clara, CA#LI-SL3
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Keywords: Advanced Micro Devices, Rancho Cordova , Analog Design Engineer Phase Lock Loop, Engineering , Santa Clara, California